CertusPro-NX

Lattice Low-power general purpose FPGA family with 10G SERDES, small packages, LPDDR4 support and high on-chip memory. Built on Lattice Nexus platform using low-power and highly reliable 28 nm FD-SOI technology.

10G SERDES at Lowest Power and Smallest Package – Up to 8 SERDES lanes supporting up to 10.3 Gbps per lane, in packages as small as 9x9 mm. Up to 4x lower power vs. similar FPGAs.

More On-chip Memory, and LPDDR4 Support – Up to 7.3 Mb of on-chip memory. Only FPGA in class with LPDDR4 support. LPDDR4, DDR3/3L, LPDDR2 supported at 1066 Mbps.

Built on Lattice Nexus platform – Class-leading power efficiency. Up to 100x higher reliability, due to 100x lower Soft Error Rate (SER) from 28 nm FD-SOI technology.

Features

Up to 100K logic cells, 7.3 Mb of embedded memory blocks (EBR, LRAM), 156 18 x 18 multipliers, 299 programmable I/O, 8 SERDES supporting up to 10.3 Gbps per lane and supporting popular protocols (10 Gig Ethernet, PCIe Gen 3, DisplayPort, SLVS-EC and CoaXPress).

Packages as small as 9x9 mm, and in ball-pitch options of 0.5, 0.8 and 1.0 mm.

Power modes – User selectable Low Power vs. High Performance modes, enabled by FD-SOI programmable back-bias.

Design security – ECDSA bitstream authentication, coupled with robust AES-256 encryption.

Fast configuration – I/O configures in 4 ms, and full-device in under 30 ms in 100K LC device.

Example Solutions

Smart SFP+ Optical Module

Implement enhanced Ethernet functions (e.g., Ethernet demarcation, OAM processing, SLA monitoring, etc.)

Compact packages as small as 9x9 mm with 10 Gigabit Ethernet support and 100K Logic Cells

Class-leading power efficiency for simpler thermal management

Hardened 10 Gigabit Ethernet PCS blocks supporting 10GBASE-R at 10.3125 Gbps, and available Ethernet MAC IP

Control Plane Security and Hardware Management

Bridge CPU via PCIe to multiple control plane peripherals (I2C, UART, GPIO), board management functions, and 10GE control plane traffic

Security functions (e.g., encryption, authentication) implemented in FPGA helps secure control plane traffic

10G SERDES supporting PCIe Gen 3 x4 (in hard IP) and 10 Gigabit Ethernet (with 10GBASE-R PCS in hard IP)

High system reliability and up-time due to 100x lower Soft Error Rate (SER) from FD-SOI technology

Fast FPGA configuration supports board management needs and PCIe boot-time requirements

Machine Vision

Vision processing and bridging for high performance SLVS-EC sensors

10G SERDES supporting SLVS-EC sensor interface, 10 GigE Vision and CoaXPress

9x9 mm small size package and class-leading power efficiency meets stringent requirements of space and thermal budget constrained camera modules

Up to 7.3 Mb on-chip memory for ISP and vision processing

LPDDR4 external memory support for optional frame buffering

Frame Grabber

Image acquisition, pre-processing and DMA over PCIe to host PC

10G SERDES supporting 10 GigE Vision, CoaXPress and PCIe Gen 3 x4 (in hard IP)

Up to 7.3 Mb on-chip memory for video processing / tagging

LPDDR4 external memory support for optional frame buffering

Smart Camera AI Processing

Offload AI processing and ISP from SoC

Interface with popular image sensors over MIPI at up to 1.5 Gbps per lane, using High Performance IO (HPIO)

Up to 7.3 Mb on-chip memory and flexible DSP resources to efficiently perform AI processing and ISP

LPDDR4 external memory support for frame buffering

Flexible output over MIPI or PCIe to SoC to enable smart device with high quality imaging

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